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1 +features q >400.0 mbps (200 mhz) switching rates q + 340mv nominal differential signaling q 3.3 v power supply q ttl compatible inputs q cold sparing all pins q ultra low power cmos technology q 3.0ns maximum, propagation delay q 0.4ns maximum, differential skew q radiation-hardened design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) and 1mrad(si) - latchup immune (let > 100 mev-cm 2 /mg) q packaging options: - 16-lead flatpack (dual in-line) q standard microcircuit drawing 5962-98651 - qml q and v compliant part introduction the ut54lvds031lv quad driver is a quad cmos differential line driver designed for applications requiring ultra low power dissipation and high data rates. the device is designed to support data rates in excess of 400.0 mbps (200 mhz) utilizing low voltage differential signaling (lvds) technology. the ut54lvds031lv accepts low voltage ttl input levels and translates them to low voltage (340mv) differential output signals. in addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state. the ut54lvds031lv and companion quad line receiver ut54lvds032lv provide new alternatives to high power pseudo-ecl devices for high speed point-to-point interface applications. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvds031lv low voltage quad driver data sheet january 8, 2003 figure 1. ut54lvds031lv quad driver block diagram d1 d2 d3 d4 d out1+ d out1- d out2+ d out2- d out3+ d out3- d out4+ d out4- d in1 d in2 d in4 d in3 en en
2 truth table pin description applications information the ut54lvds031lv driver?s intended use is primarily in an uncomplicated point-to-point configuration as is shown in figure 3. this configuration provides a clean signaling environment for quick edge rates of the drivers. the receiver is connected to the driver through a balanced media such as a standard twisted pair cable, a parallel pair cable, or simply pcb traces. typically, the characteristic impedance of the media is in the range of 100 w . a termination resistor of 100 w should be selected to match the media and is located as close to the receiver input pins as possible. the termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. other configurations are possible such as a multi- receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. the ut54lvds031lv differential line driver is a balanced current source design. a current mode driver, has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. the current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in figure 3. ac or unterminated configurations are not allowed. the 3.4ma loop current will develop a differential voltage of 340mv across the 100 w termination resistor which the receiver detects with a 240mv minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340mv - 100mv = 240mv)). the signal is centered around +1.2v (driver offset, v os ) with respect to ground as shown in figure 4. note: the steady-state voltage (v ss ) peak-to-peak swing is twice the differential voltage (v od ) and is typically 680mv. enables input output en en d in d out+ d out- l h x z z all other combinations of enable inputs l l h h h l pin no. name description 1, 7, 9, 15 d in driver input pin, ttl/cmos compatible 2, 6, 10, 14 d out+ non-inverting driver output pin, lvds levels 3, 5, 11, 13 d out- inverting driver output pin, lvds levels 4 en active high enable pin, or-ed with en 12 en active low enable pin, or-ed with en 16 v dd power supply pin, +3.3v + 0.3v 8 v ss ground pin figure 2. ut54lvds031lv pinout ut54lvds031lv driver 16 15 14 13 12 11 10 9 v dd d in4 d out4+ d out4- en d out3- d out3+ d in3 1 d in1 2 d out1+ 3 d out1- 4 en 5 d out2- 6 d out2+ 7 d in2 8 v ss enable data input 1/4 ut54lvds031lv 1/4 ut54lvds032lv + - data output figure 3. point-to-point application rt 100 w
3 the current mode driver provides substantial benefits over voltage mode drivers, such as an rs-422 driver. its quiescent current remains relatively flat versus switching frequency. whereas the rs-422 voltage mode driver increases exponentially in most cases between 20 mhz - 50 mhz. this is due to the overlap current that flows between the rails of the device when the internal gates switch. whereas the current mode driver switches a fixed current between its output without any substantial overlap current. this is similar to some ecl and pecl devices, but without the heavy static i cc requirements of the ecl/pecl design. lvds requires 80% less current than similar pecl devices. ac specifications for the driver are a tenfold improvement over other existing rs- 422 drivers. the three-state function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. d in d out- d out+ single-ended d out+ - d out- differential output v 0d 3v 0v v oh v os v ol +v od -v od 0v 0v (diff.) v ss figure 4. driver output levels note: the footprint of the ut54lvds031lv is the same as the industry standard quad differential (rs-422) driver.
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and life test. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.3 to 4.0v v i/o voltage on any pin during operation -0.3 to (v dd + 0.3v) voltage on any pin during cold spare -.3 to 4.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.25 w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6v t c case temperature range -55 to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics 1, 2 (v dd = 3.3v + 0.3v; -55 c < t c < +125 c) notes: 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenc ed to ground except differential voltages. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. 3. guaranteed by characterization. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v dd v v il low-level input voltage (ttl) v ss 0.8 v v ol low-level output voltage r l = 100 w 0.925 v v oh high-level output voltage r l = 100 w 1.650 v i in input leakage current v in = v dd or gnd, v dd = 3.6v -10 +10 m a i cs cold spare leakage current v in =3.6v, v dd =v ss -20 +20 ma v od 1 differential output voltage r l = 100 w (figure 5) 250 400 mv d v od 1 change in magnitude of v od for complementary output states r l = 100 w (figure 5) 35 mv v os offset voltage r l = 100 w , 1.125 1.450 v d v os change in magnitude of v os for complementary output states r l = 100 w (figure 5) 25 mv v cl 3 input clamp voltage i cl = +18ma -1.5 v i os 2, 3 output short circuit current v in = v dd , v out+ = 0v or v in = gnd, v out- = 0v 9.0 ma i oz 3 output three-state current en = 0.8v and en = 2.0 v, v out = 0v or v dd, v dd = 3.6v -10 +10 ma i ccl 3 loaded supply current, drivers enabled r l = 100 w all channels v in = v dd or v ss (all inputs) 20.0 ma i ccz 3 loaded supply current, drivers disabled d in = v dd or v ss en = v ss , en = v dd 4.0 ma vos voh vol + 2 --------------------------- = ? ??
6 figure 5. driver v od and v os test circuit or equivalent circuit d d in d out- d out+ 10pf driver enabled generator 50 w r l = 100 w v od 10pf
7 ac switching characteristics 1, 2, 3 (v dd = +3.3v + 0.3v, t a = -55 c to +125 c) notes: 1. channel-to-channel skew is defined as the difference between the propagation delay of the channel and the other channels in t he same chip with an event on the inputs. 2. generator waveform for all tests unless otherwise specified: f = 1 mhz, z o = 50, t r < 1ns, and t f < 1ns. 3. c l includes probe and jig capacitance. 4. guaranteed by characterization 5. chip to chip skew is defined as the difference between the minimum and maximum specified differential propagation delays. 6. may be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter. symbol parameter min max unit t phld 6 differential propagation delay high to low (figures 6 and 7) 0.3 3.0 ns t plhd 6 differential propagation delay low to high (figures 6 and 7) 0.3 3.0 ns t skd 4 differential skew (t phld - t plhd ) (figures 6 and 7) 0 0.4 ns t sk1 4 channel-to-channel skew 1 (figures 6 and 7) 0 0.5 ns t sk2 4 chip-to-chip skew 5 (figure 6 and 7) 2.7 ns t tlh 4 rise time (figures 6 and 7) 1.5 ns t thl 4 fall time (figures 6 and 7) 1.5 ns t phz 4 disable time high to z (figures 8 and 9) 5.0 ns t plz 4 disable time low to z (figures 8 and 9) 5.0 ns t pzh 4 enable time z to high (figures 8 and 9) 7.0 ns t pzl 4 enable time z to low (figures 8 and 9) 7.0 ns
8 d d in d out- d out+ driver enabled generator 50 w r l = 100 w figure 6. driver propagation delay and transition time test circuit or equivalant circuit 10pf 10pf d in d out- d out+ v diff t phld v dd 0v v oh v ol 0v v diff = d out+ - d out- 0v (differential) 1.5v t thl 20% 80% 0v 20% 80% t tlh t plhd 1.5v figure 7. driver propagation delay and transition time waveforms
9 d v dd v ss d in en generator 50 w en r l =100 w d out+ d out- figure 8. driver three-state delay test circuit or equivalant circuit 10pf 10pf en when en = v dd en when en = v ss or d out+ when d in =v dd d out- when d in = v ss d out+ when d in = v ss d out- when d in = v dd t plz t pzl 50% 50% v ol v os v os v oh 0v v dd 0v v dd 1.5v 1.5v 1.5v 1.5v 50% t pzh t phz figure 9. driver three-state delay waveform 50%
10 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance to mil-prf-38535. 4. package dimensions and symbols are similar to mil-std-1835 variation f-5a. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 10. 16-pin ceramic flatpack packaging
11 ordering information ut54lvds031lv quad driver: ut 54lvds031lv - * * * * * device type: ut54lvds031lv lvds driver access time: not applicable package type: (u) = 16-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
12 ut54lvds031lv quad driver: smd 5962 - * * * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) drawing number: 5962-98651 device type 02 = lvds driver, 300k, 500k and 1m rad(si) 03 = lvds driver, 100k rad(si) class designator: (q) = qml class q (v) = qml class v case outline: (y) = 16 lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) 98651 ** notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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